Design of 8-4 and 9-4 Compressors Forhigh Speed Multiplication
- 1 School of Electrical Engineering, VIT University, Vellore, India
Abstract
This study presents higher order compressors which can be effectively used for high speed multiplications. The proposed compressors offer less delay and area. But the Energy Delay Product (EDP) is slightly higher than lower order compressors. The performance of 8×8, 16×16 and 24×24 multipliers using the proposed higher order compressors has been compared with the same multipliers using lower order compressors and found that the new structures can be used for high speed multiplications. These compressors are simulated with Cadence RTL complier at a temperature of 25°C with the supply voltage of 1.2 V.
DOI: https://doi.org/10.3844/ajassp.2013.893.900
Copyright: © 2013 R. Marimuthu, Dhruv Bansal, S. Balamurugan and P. S. Mallick. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
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Keywords
- Binary Multiplier
- Compressors
- High Speed Adder
- Area Efficient
- Energy Delay Product